Connector - TI-99/4A Card Slot

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Pin	Name	Direction	Description
		---
1	+8V	---	+5V 3-T regulator voltage supply (about +8V)
		---
2	+8V	---	+5V 3-T regulator voltage supply (about +8V)
		---
3	GND	---	Ground
		---
4	READYA	---	System ready (10K pull-up to +5V)
		---
5	GND	---	Ground
		---
6	RESET*	Output	System reset (active low)
		---
7	GND	---	Ground
		---
8	SCLK	---	System clock (not connected)
		---
9	LCP*	---	CPU indicator 1=TI99 0=2nd generation (not connected)
		---
10	AUDIO	Input	Input audio (=AUDIOIN)
		---
11	RDBENA*	Input	Active low: enable flex cable data bus drivers (1K pull-up)
		---
12	PCBEN		PCB enable for burn-in (always High)
		---
13	HOLD*		Active low CPU hold request (always High)
		---
14	IAQHA	---	IAQ [or] HOLDA (logical or)
		---
15	SENILA*		Interrupt level A sense enable (always High)
		---
16	SENILB*		Interrupt level B sense enable (always High)
		---
17	INTA*	Input	Active low interrupt level A (=EXTINT*)
		---
18	LOAD*	---	Unmaskable interrupt (not connected)
		---
19	D7	---	Data bit 7 (LSB)
		---
20	GND	---	Ground
		---
21	D5	---	Data bit 5
		---
22	D6	---	Data bit 6
		---
23	D3	---	Data bit 3
		---
24	D4	---	Data bit 4
		---
25	D1	---	Data bit 1
		---
26	D2	---	Data bit 2
		---
27	GND	---	Ground
		---
28	D0	---	Data bit 0 (MSB)
		---
29	A14	Output	Address bit 14
		---
30	A15	Output	Address bit 15 (LSB). Also CRU output bit.
		---
31	A12	Output	Address bit 12
		---
32	A13	Output	Address bit 13
		---
33	A10	Output	Address bit 10
		---
34	A11	Output	Address bit 11
		---
35	A8	Output	Address bit 8
		---
36	A9	Output	Address bit 9
		---
37	A6	Output	Address bit 6
		---
38	A7	Output	Address bit 7
		---
39	A4	Output	Address bit 4
		---
40	A5	Output	Address bit 5
		---
41	A2	Output	Address bit 2
		---
42	A3	Output	Address bit 3
		---
43	A0	Output	Address bit 0 (MSB)
		---
44	A1	Output	Address bit 1
		---
45	AMB		Extra address bit. Always High.
		---
46	AMA		Extra address bit. Always High.
		---
47	GND	---	Ground
		---
48	AMC		Extra address bit. Always High.
		---
49	GND	---	Ground
		---
50	CLKOUT*	Output	Inversion of phase 3 clock (=PHI3*)
		---
51	CRUCLK*	Output	Inversion of TMS9900 CRUCLOCK pin
		---
52	DBIN	Output	Active high = read memory
		---
53	GND	---	Ground
		---
54	WE*	Output	Write Enable (derived from TMS9900 WE* pin)
		---
55	CRUIN	Input	CRU input bit to TMS9900
		---
56	MEMEN*	Output	Memory access enable (active low)
		---
57	-12V	---	-12 Volts 3-T regulator supply voltage (about -16V)
		---
58	-12V	---	-12 Volts 3-T regulator supply voltage (about -16V)
		---
59	+12V	---	+12 Volts 3-T regulator supply voltage (about +16V)
		---
60	+12V	---	+12 Volts 3-T regulator supply voltage (about +16V)

Direction is computer relative world.

Notes:

Signals buffered by 74LS244 in connection card: A0-A15, DBIN, MEMEN*, WE*, CLRCLK*, RESET*, CLKOUT.
Unbuffered signals: CRUIN, INTA*, AUDIOIN, READY
Data bus is buffered by two 74LS245 (one at each end of the cable),driven by RDBENA (direction set by DBIN).
All signals must be re-buffered on each card.
Always High lines (AMA, AMB, AMC, SENILA*, SENILB*, PCBEN, HOLD*) are pulled up to +5 Volts by 47 Ohms resistors.

Source: HW-Book 2001-06-08
Last modified: 2007-06-27 14:22:53.0
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