2024-04-18 07:23:33 - Not logged in - de

Connector - ISA

ISA=Industry Standard Architecture

62+36 PIN EDGE CONNECTOR MALE at the card.
62+36 PIN EDGE CONNECTOR FEMALE at the computer.

	(at the computer)
	(at the card)

Pin	Name	Direction	Description
A1	/I/O CH CK	Input	I/O channel check; active low=parity error
A2	D7	---	Data bit 7
A3	D6	---	Data bit 6
A4	D5	---	Data bit 5
A5	D4	---	Data bit 4
A6	D3	---	Data bit 3
A7	D2	---	Data bit 2
A8	D1	---	Data bit 1
A9	D0	---	Data bit 0
A10	I/O CH RDY	Input	I/O Channel ready, pulled low to lengthen memory cycles
A11	AEN	Output	Address enable; active high when DMA controls bus
A12	A19	Output	Address bit 19
A13	A18	Output	Address bit 18
A14	A17	Output	Address bit 17
A15	A16	Output	Address bit 16
A16	A15	Output	Address bit 15
A17	A14	Output	Address bit 14
A18	A13	Output	Address bit 13
A19	A12	Output	Address bit 12
A20	A11	Output	Address bit 11
A21	A10	Output	Address bit 10
A22	A9	Output	Address bit 9
A23	A8	Output	Address bit 8
A24	A7	Output	Address bit 7
A25	A6	Output	Address bit 6
A26	A5	Output	Address bit 5
A27	A4	Output	Address bit 4
A28	A3	Output	Address bit 3
A29	A2	Output	Address bit 2
A30	A1	Output	Address bit 1
A31	A0	Output	Address bit 0
B1	GND	---	Ground
B2	RESET	Output	Active high to reset or initialize system logic
B3	+5V	---	+5 VDC
B4	IRQ2	Input	Interrupt Request 2
B5	-5VDC	---	-5 VDC
B6	DRQ2	Input	DMA Request 2
B7	-12VDC	---	-12 VDC
B8	/NOWS	Input	No WaitState
B9	+12VDC	---	+12 VDC
B10	GND	---	Ground
B11	/SMEMW	Output	System Memory Write
B12	/SMEMR	Output	System Memory Read
B13	/IOW	Output	I/O Write
B14	/IOR	Output	I/O Read
B15	/DACK3	Output	DMA Acknowledge 3
B16	DRQ3	Input	DMA Request 3
B17	/DACK1	Output	DMA Acknowledge 1
B18	DRQ1	Input	DMA Request 1
B19	/REFRESH	---	Refresh
B20	CLOCK	Output	System Clock (67 ns, 8-8.33 MHz, 50% duty cycle)
B21	IRQ7	Input	Interrupt Request 7
B22	IRQ6	Input	Interrupt Request 6
B23	IRQ5	Input	Interrupt Request 5
B24	IRQ4	Input	Interrupt Request 4
B25	IRQ3	Input	Interrupt Request 3
B26	/DACK2	Output	DMA Acknowledge 2
B27	T/C	Output	Terminal count; pulses high when DMA term. count reached
B28	ALE	Output	Address Latch Enable
B29	+5V	---	+5 VDC
B30	OSC	Output	High-speed Clock (70 ns, 14.31818 MHz, 50% duty cycle)
B31	GND	---	Ground
		---
C1	SBHE	---	System bus high enable (data available on SD8-15)
C2	LA23	---	Address bit 23
C3	LA22	---	Address bit 22
C4	LA21	---	Address bit 21
C5	LA20	---	Address bit 20
C6	LA18	---	Address bit 19
C7	LA17	---	Address bit 18
C8	LA16	---	Address bit 17
C9	/MEMR	---	Memory Read (Active on all memory read cycles)
C10	/MEMW	---	Memory Write (Active on all memory write cycles)
C11	SD08	---	Data bit 8
C12	SD09	---	Data bit 9
C13	SD10	---	Data bit 10
C14	SD11	---	Data bit 11
C15	SD12	---	Data bit 12
C16	SD13	---	Data bit 13
C17	SD14	---	Data bit 14
C18	SD15	---	Data bit 15
D1	/MEMCS16	Input	Memory 16-bit chip select (1 wait, 16-bit memory cycle)
D2	/IOCS16	Input	I/O 16-bit chip select (1 wait, 16-bit I/O cycle)
D3	IRQ10	Input	Interrupt Request 10
D4	IRQ11	Input	Interrupt Request 11
D5	IRQ12	Input	Interrupt Request 12
D6	IRQ15	Input	Interrupt Request 15
D7	IRQ14	Input	Interrupt Request 14
D8	/DACK0	Output	DMA Acknowledge 0
D9	DRQ0	Input	DMA Request 0
D10	/DACK5	Output	DMA Acknowledge 5
D11	DRQ5	Input	DMA Request 5
D12	/DACK6	Output	DMA Acknowledge 6
D13	DRQ6	Input	DMA Request 6
D14	/DACK7	Output	DMA Acknowledge 7
D15	DRQ7	Input	DMA Request 7
D16	+5 V	---
D17	/MASTER	Input	Used with DRQ to gain control of system
D18	GND	---	Ground

Note: Direction is Motherboard relative ISA-Cards.

Note: B8 was /CARD SLCDTD on the XT. Card selected, activated by cards in XT's slot J8

Source: HW-Book 2001-06-08
Last modified: 2007-06-27 14:22:49.0
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File last modified 2024-02-15 23:07:43